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* 1. Liang, J. et al. Atomistic to circuit level modeling of defective doped SWCNTs with contacts for on-chip interconnect application. 2017 IEEE 12th Nanotechnol. Mater. Devices Conf. NMDC 2017 2018-Janua, 66–67 (2018). | * 1. Liang, J. et al. Atomistic to circuit level modeling of defective doped SWCNTs with contacts for on-chip interconnect application. 2017 IEEE 12th Nanotechnol. Mater. Devices Conf. NMDC 2017 2018-Janua, 66–67 (2018). |